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SI3404 data sheet fully-integrated ieee 802.3 type 1-compliant poe pd interface and high-efficiency switching regulator with compact footprint the SI3404 integrates all power management and control functions required in a pow- er-over-ethernet (poe) powered device (pd) application. these devices convert the high voltage supplied over the 10/100/1000base-t ethernet connection to a regulated, low-voltage output supply. the optimized architecture of this device minimizes the solu- tion footprint and external bom cost and enables the use of low-cost external compo- nents while maintaining high performance. the SI3404 integrates a transient surge suppressor. the switching power fet and all associated functions are also integrated. the integrated, current mode controlled switching regulator supports isolated or non- isolated flyback and buck converter topologies. the switching frequency for the regula- tor is tunable with a simple external resistor value to help avoid unwanted harmonics for better emissions control. this device fully supports the ieee 802.3at specification for type 1, single-event classi- fication. standard external resistors provide the proper ieee 802.3 signatures for the detection function and programming of the classification mode, and internal startup cir- cuits ensure well-controlled soft-start initial operation of both the hotswap switch and the voltage regulator. the SI3404 is available in a low-profile, 20-pin, 4 x 4 mm qfn package. key features ? type 1 (poe) power ? ieee 802.3at type 1 compliance ? current mode dc-dc converter ? tunable switching frequency ? transformer bias winding support ? auxiliary adapter support ? integrated hotswap fet and switching fet ? 120 v absolute max voltage performance ? extended C40 to +85 c temperature ? compact rohs-compliant 4 mm x 4 mm qfn package applications ? voice over ip telephones ? wireless access points ? security and surveillance ip cameras ? point-of-sale terminals ? internet appliances ? network devices silabs.com | building a more connected world. preliminary rev. 0.5 this information applies to a product under development. its characteristics and specifications are subject to change without notice.
1. ordering guide table 1.1. SI3404 ordering guide ordering part number package temperature range (ambient) applications SI3404-a-gm 4 x 4 mm 20-qfn pb-free, rohs-compliant C40 to 85 c extended all purposes SI3404 data sheet ordering guide silabs.com | building a more connected world. preliminary rev. 0.5 | 2
table of contents 1. ordering guide ..............................2 2. system overview ..............................4 2.1 block diagram ..............................4 2.2 power over ethernet (poe) line-side interface ...................4 2.2.1 surge protection ...........................4 2.2.2 telephony protection .........................4 2.2.3 detection and classification .......................5 2.3 hotswap switch .............................5 2.4 hssw state machine ...........................6 2.5 dc to dc converter ............................7 2.5.1 average current sensing, overcurrent, and low-current detection ..........7 2.6 tunable oscillator ............................8 2.7 regulators ...............................8 2.8 external wall support ...........................8 3. application examples ............................9 4. electrical specifications .......................... 11 5. pin descriptions ............................. 15 5.1 detailed pin descriptions .......................... 16 6. packaging ............................... 19 6.1 package outline: SI3404 .......................... 19 6.2 land pattern: SI3404 ........................... 21 7. SI3404 top marking ............................ 23 8. revision history ............................. 24 silabs.com | building a more connected world. preliminary rev. 0.5 | 3
2. system overview the following block diagrams will give the designer a sense for the internal arrangement of functional blocks, plus their relationships to external pins. the block diagrams are followed by a description of the features of these integrated circuits. 2.1 block diagram vpos vneg detection rdet oscs fixed: 250khz adjustable: 100...500khz class poe controller hot-swap controller thermal protection hso 5v regulator rfreq vdd rcl current mode pwm controller thermal protection vss swo erout fbl fbh tvs 100v hssw 250khz 250khz vpos-1.32v vss+1.32v i bias start isns i avg dc/dc sw vt15 aux winding support figure 2.1. SI3404 block diagram 2.2 power over ethernet (poe) line-side interface the poe line interface consists of external diode bridges, internal surge protection, and protocol interface support for detection and classification. the chip features active protection against surge transients and accidentally applied telephony voltages. 2.2.1 surge protection the surge protection circuit is activated if the vpos-vneg voltage exceeds t prot and the hotswap switch is off (dc-dc is not pow- ered). if the hotswap switch is on, the surge power is sunk in the dc-dcs input capacitance. the internal surge protection can be overridden with an external tvs if higher than specified surge conditions need be tolerated. the external surge device must be connected in parallel to the internal one; therefore, the designer must ensure that the external surge protection will activate prior to the internal surge protection. 2.2.2 telephony protection the SI3404 provides protection against telephony ringing voltage. the telephony ringing is much longer than the surge pulse but it has less energy, therefore, the SI3404 has a switch parallel with the supply (vpos and vneg). when the protection circuit is activated, it turns on the telephony switch; the ringing energy then dissipates on this switch and ringing generator resistance (> 400 ?). SI3404 data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 4
2.2.3 detection and classification when the SI3404 is connected via ethernet cable to a pse-enabled ethernet switch, it has to provide a characteristic resistance (~25 k) to the pse in a given voltage range (2.7C10.1 v). this is called detection. after the pse detects the pd, the pse increases the voltage above the classification threshold 14.5 v. then, the pd provides the classification current to inform the pse about its required power class (class 1, 2, 3, or 4). type 1 pses cannot provide enough power for a class 4 pd. type 2 pses have additional voltage steps before switching on the pd. after an initial classification voltage pulse, the type 2 pse reduces the voltage below the mark threshold level (10 v) then raises it up again to the class event range. last, before switching on the dcdc it reduces the voltage again. the SI3404 is a type 1 pd, thus it does not respond to the additional voltage steps pertaining to type 2. figure 2.2. powered device voltages 2.3 hotswap switch the internal hotswap switch (hssw) is turned on (conducting) when the poe interface voltage goes above v uvlo_r . it provides limited inrush current until the dcdc side capacitor is charged. the hotswap switch turns off (open) if voltage on the hssw switch is greater than v hssw_off . in overload, the hotswap switch goes into current-limiting mode with a current limit of i ovl . it will turn back on after t waithssw elapses and the dc-dc input capacitor is recharged, meaning the hso-vneg voltage is less than v hssw_on . SI3404 data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 5
2.4 hssw state machine the hssw operates as simple 4-state state machine: figure 2.3. hotswap switch 4-state machine note: internal signal names are shown in this figure, not to be confused with external pin names. for the below discussion, i load is the switch current, and v hssw is the voltage drop of the switch. in other words, v hssw = hso C vneg. all the voltage, current and time limits of the above diagram are typical values. off state hssw turn-on is controlled by uvlo, the undervoltage lockout feature. when uvlo is engaged, the hssw is off. in this state, the hssw is in idle mode, vneg and hso pins are disconnected. in normal operation, a complete detect/classification procedure pre- cedes the hssw turn-on, and the control of this sequence is implemented in the state machine logic of the chip. inrush state after the controller enables the hssw, the block starts operation in the inrush state. in this state the switch itself is not directly turned on, but operating in a closed-loop current limit mode to avoid high current peaks during the charging of the primary bypass cap of the dc to dc converter. if the v hssw voltage drops below 380 mv (meaning the bypass cap is 99% charged), the hssw will change state to on. on state in on state, the hssw switch is directly turned on. the hssw circuit continuously monitors v hssw . hssw will change to overload state if v hssw voltage increases over 3.6 v for at least 140 s. overload state in overload state the hssw operates in closed-loop low current limit mode. if the v hssw voltage drops below 360 mv again, and the hssw has been in the overload state for at least 80 ms, the hssw will change back to the on state. SI3404 data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 6
2.5 dc to dc converter the dc-to-dc converter is current-controlled for easier compensation and more robust protection of circuit magnetics. the controller has the following features: ? high- and low-side feedback (supports buck and flyback topologies). ? <1 internal switching fet ? overcurrent detection ? cycle skipping at low current and short circuit conditions swo erout fbl fbh v11 syncl drv 1.32v g mh 100s g ml 100s g mpeak 50s 1.32v i peak limit vdd drv non overlap driver 1:1072 comp clipping blanking time vdd r q q comp 270mv 50mv comp lpf isns osc c softs soft start v erout limit reset loop comp vpos i avg limit low current detect pd vdd or and slope compensation s short detect pd short detect vss vpos vdd figure 2.4. SI3404 dc-dc converter feedback to the dcdc converter can be provided in three ways: ? high side, referenced to vpos, connected to fbh pin (buck converter) ? low side, referenced to vss, connected to fbl pin (nonisolated flyback) ? directly to erout pin by a voltage to current converter (isolated flyback) the erout pin provides current output (if fbl or fbh is used) and voltage input. also, the loop compensation impedance is connec- ted to erout. the active voltage range is v erout , which is proportional to the converter peak current. the converter startup is not configurable; soft start is accomplished by internal circuitry. soft start time is t softstart . the intelligent soft start circuit dynamically adjusts the soft start time depending on the connected load. 2.5.1 average current sensing, overcurrent, and low-current detection the application average current is sensed by an external resistor (r sense ) connected between vss and isns. overcurrent is detected and triggered when the voltage on the sense resistor exceeds v isns_ovc . sizing the resistor allows the designer to set the overcurrent limit according to application needs. when overcurrent is triggered, the dcdc controller goes into reset until the overcurrent resolves. when the overcurrent is no longer present, the controller starts up again with softstart. SI3404 data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 7
2.6 tunable oscillator the dcdc frequency can be fixed to 250 khz or tunable by an external resistor. the tuning resistor must be connected between the r freq pin and vpos. if r freq is shorted to vpos, the fixed frequency oscillator will provide the clock, f oscint , to the dcdc converter; otherwise, the resistor will determine the frequency as shown in the curve below. figure 2.5. r freq frequency selector diagram 2.7 regulators the chip provides a 5 v output to power leds or optocouplers. this is a closed-loop regulator, which ensures accurate output voltage. the 5 v regulator is supplied by an internal 11 v open loop regulator. the 11 v regulator is supplied by a coarse regulator, which is also open-loop. with the SI3404, the vt15 pin can be used to supply this regulator from an optional auxiliary transformer bias winding. the advantage of doing so is additional power saving. the application must be designed to ensure that the absolute maximum rating volt- age for the vt15 pin is not exceeded. 2.8 external wall support the SI3404 allows the use of a range of external wall adapters as a primary or secondary supply. for details on adapter connection, please refer to "an1130: using the si3406/si34061/si34062 poe+ and SI3404 poe pd controller in isolated and non-isolated de- signs". SI3404 data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 8
3. application examples the following diagrams demonstrate the ease of use and straightforward bom of the SI3404 powered device ic. detailed reference designs are available in evaluation kit user guides. also refer to "an1130: using the si3406/si34061/si34062 poe+ and SI3404 poe pd controller in isolated and non-isolated designs". rfreq rfreq vpos vss cin vpos rdet rdet rclass rclass erout fbl swo vdd vneg SI3404 vneg cdet vss vss vss vss rcomp ccomp cout r1 r2 vout c vin vin rsense isns hso vss vt15 bias vss figure 3.1. SI3404 non-iso flyback application diagram rfreq rfreq vpos cin vpos rdet rdet rclass rclass erout swo vdd vneg SI3404 vneg cdet vss rcomp1 ccomp1 cout vout vin vin rsense hso vss vt15 bias vss rcomp2 ccomp2 tlv431 r2 r1 gndi *gndi = isolated ground gndi vss vss c vss isns figure 3.2. SI3404 iso flyback application diagram SI3404 data sheet application examples silabs.com | building a more connected world. preliminary rev. 0.5 | 9
rcomp rfreq rfreq vpos vss cin vpos rdet rdet rclass rclass erout swo vdd vneg SI3404 vneg cdet cout vout vin vin rsense isns hso vss vss c r2 r1 vss fbh ccomp d l figure 3.3. SI3404 buck application diagram SI3404 data sheet application examples silabs.com | building a more connected world. preliminary rev. 0.5 | 10
4. electrical specifications table 4.1. absolute maximum ratings 1 type description min max units voltage vneg-vss, vpos- vneg, hso 2 , rdet 3 C0.7 100 v swo-vss C0.7 120 v isns C1 1 v low voltage pins: fbh 3 , erout, fbl, rcl 2 , rfreq 3 C0.7 6 v mid voltage pins: vt15 C0.7 18 v peak current vpos Ctbd tbd a temperature storage temperature C65 150 c ambient operating temperature C40 85 note: 1. unless otherwise noted, all voltages referenced to vss. permanent device damage may occur if the maximum ratings are excee- ded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. expo- sure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. voltage referenced to vneg. 3. voltage referenced to vpos. SI3404 data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 11
table 4.2. recommended operating conditions symbol parameter (condition) min typ max unit v port vport = vpos C vneg 1.5 57 v v hv_op vneg-vss, vneg-hso, vpos- vss 1.5 57 v v lv_op vpos referred low voltage pins: rfreq, rdet, fbh C5.5 0 v v lv_op vss referred low voltage pins: vdd, fbl, erout 0 5.5 v v isns_op vss referred current sensing pin: isns C0.5 0.5 v v lv_op vneg referred low voltage pins: rcl 0 5.5 v v mv_vt15 vss referred medium voltage pin vt15 1 12 14.5 16.5 v i avg allowable continuous current on swo, vss, hso, vneg 600 ma i peak peak current on swo, vss, hso, vneg max 75 ms 5% duty cycle 683 ma note: 1. v mv_vt15 is relevant for SI3404 only when an external auxiliary bias winding from the primary side of the transformer is being used to improve power conversion efficiency. this can be left undriven, in which case an internal regulator will be used. SI3404 data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 12
table 4.3. electrical characteristics symbol parameter (condition) min typ max unit poe protocol detection v det detection voltage (at v port ) 1.5 8.9 v classification v reset classification reset (at v port ) 0 1.61 v v class classification voltage (at v port ) 13.4 21.4 v i portclass class 0 (r class > 681 ) 0 4 ma class 1 (r class = 140 @ 1%) 9 12 ma class 2 (r class = 75 @ 1%) 17 20 ma class 3 (r class = 48.7 @ 1%) 26 30 ma power on and uvlo v uvlo_r hotswap closed and converter on 37 v v uvlo_f hotswap open and converter off 32 v thermal characteristics t shd thermal shutdown 160 c t hyst thermal shutdown hysteresis 20 c on-chip transient voltage suppression/protection t prot tvs protection activation voltage (vpos-vneg) 100 v hotswap switch i inrush inrush current 100 170 200 ma i maxhssw maximum continuous operating cur- rent 600 ma v hssw_on switch on voltage 380 mv v hssw_off switch off voltage, hssw goes to overload cycle 3.5 v i ovl switch current limit in overload state 8.7 10.5 12.4 ma t waithssw wait time in overload 80 96 116 ms r onhssw internal hotswap drain-source resist- ance while on 0.65 1.5 2.9 ? dc-dc i swopeak peak current limit of internal fet (swo pin) 2.1 2.7 a f oscint using internal oscillator 250 khz f oscext using external oscillator, tunable on pin rfreq 100 500 khz SI3404 data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 13
symbol parameter (condition) min typ max unit duc output duty cycle of pwm tbd 75 % v fbref fbh (referenced to vpos) and fbl (referenced to vss) reference volt- age 1.32 v v erout operating voltage range of error in- put 1 4 v v isns_ovc overcurrent limit voltage on isns (ref. to vss) C270 mv t softstart startup time 4 ms r ondcdc internal dcdc switching fet drain- source resistance while on 0.9 1.2 ? regulators vt15 override internal regulator with transformer winding 13 16.5 v vdd 5 v regulated output 4.85 5.1 5.46 v vdd ilim dc current limit of vdd 9.7 11.2 12.9 ma c reg filter capacitor on vdd 100 nf power dissipation p intmax dc-dc max power internal fet 1.2 1.5 w p max total chip power tbd tbd w i portop operating current (v port 57 v; 250 khz) 3 4 ma package thermal characteristics ja-eff qfn20 1 46.8 c/w note: 1. assumes 4-layer pcb and approximately 1.2 w input power. SI3404 data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 14
5. pin descriptions isns fbh erout vdd rdet rcl rfreq hso nc vneg (epad) 6 7 8 9 10 1 2 3 4 fbl 5 15 14 13 12 11 nc vpos nc nc nc 20 19 18 17 16 vt15 nc swo vss nc figure 5.1. SI3404 pinout table 5.1. pin descriptions SI3404 pins name ref dir. vrange description 1 isns vss i C0.5 to 0 chip current sense resistor input 2 fbh vpos i 0C5 high side (vpos referred) dcdc feedback (buck converter) 3 erout vss io 0C5 error amplifier current output, compensation impedance input 4 fbl vss i 0C5 low side (ground referenced) dcdc feedback (flyback con- verter) 5 vdd vss o 0C5 5v regulator output 6 rdet vpos io 0C100 detection resistor 8 hso vneg io 0C100 hot swap switch output 9 rcl vneg io 0C5 classification resistor 10 rfreq vpos io 0C5 oscillator frequency tuning resistor, tie to vpos to select default freq 13 vpos io 0C100 rectified high-voltage supply positive rail 16 vt15 vss i 0C16.5 dcdc transformer auxiliary winding input 18 swo vss o 0C120 internal dcdc switch output (nmos drain) 19 vss io 0 dcdc converter primary ground epad vneg io 0 rectified high voltage supply ground 7, 11, 12, 14, 15, 17, 20 nc do not connect SI3404 data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 15
5.1 detailed pin descriptions table 5.2. circuit equivalent and description of die pads pin name detailed description circuit detail isns average current sense resistor input. the resistor value will set the maxi- mum allowed current for the application. the overcurrent threshold voltage v isns_ovc . note that this pin voltage goes below vss. fbh high side dcdc feedback input. need to be tied to vpos when not used. see vfbref. erout dcdc converter error output; current out, voltage sense. loop compensating impedance should be connected here. i erout = (v fbh C v fbref ) x 50 a or i erout = (v fbl C v fbref ) x 50 a fbl low side dcdc feedback input. need to be tied to vss when not used. see v fbref vdd regulated 5 v relative to vss. there is no foldback characteristic, reaching vdd ilim the output voltage decreases. the regulator needs c reg external capacitance. SI3404 data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 16
pin name detailed description circuit detail rcl classification resistor input. for class 0 this pin can be left floating. pin is active only at time of classification. rfreq used for adjusting the oscillator frequency. the frequency is inversely proportional to the value of the connected resis- tor. vpos, vneg main chip input power. note that vneg (the epad on the bottom of the chip) also provides thermal relief. hso hotswap switch output. the switch shorts the vneg and hso pins, and in- cludes several other functions. see hotswap switch section for details. rdet the user has to tie the rdet resistor between this pin and vpos. during detection, a high voltage switch pulls down rdet to vneg. after detection, the reference block uses rdet as absolute chip current reference, forcing C750 mv relative to vpos, creating 30 a for the internal blocks. SI3404 data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 17
pin name detailed description circuit detail vt15 vt15 is input for an optional 15 v supply generated by an auxiliary trans- former bias winding. if the bias winding voltage is lower than vt15, the in- ternal 15 v coarse regulator will provide the current for the 11 v regulator. swo dcdc converter switching transistor drain output, vmax = 120 v. vss dc-dc converter ground. SI3404 data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 18
6. packaging 6.1 package outline: SI3404 the figure below illustrates the package details for the SI3404. the table lists the values for the dimensions shown in the illustration. figure 6.1. 20-pin, qfn package table 6.1. package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.55 2.60 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.50 2.60 2.70 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.10 SI3404 data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 19
dimension min nom max note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. SI3404 data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 20
6.2 land pattern: SI3404 the figure below illustrates the land pattern details for the SI3404. the table lists the values for the dimensions shown in the illustration. figure 6.2. 20-pin, qfn land pattern table 6.2. land pattern dimensions dimension min max c1 3.90 4.00 c2 3.90 4.00 e 0.50 bsc x1 0.20 0.30 x2 2.55 2.65 y1 0.65 0.75 y2 2.55 2.65 SI3404 data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 21
dimension min max note: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 mm minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 2x2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI3404 data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 22
7. SI3404 top marking figure 7.1. SI3404 top marking table 7.1. SI3404 top marking explanation mark method: laser pin 1 mark: circle = 0.50 mm diameter (lower-left corner) font size: 0.6 point (24 mils) line 1 mark format: device part number SI3404 line 2 mark format: tttttt trace code (assigned by the assembly subcontractor) line 3 mark format: yy = year ww = work week assembly year assembly week SI3404 data sheet SI3404 top marking silabs.com | building a more connected world. preliminary rev. 0.5 | 23
8. revision history revision 0.5 february, 2018 ? updated 2. system overview and 3. application examples . ? added theory of operation and application content. ? updated table 4.1 absolute maximum ratings 1 on page 11 , table 4.2 recommended operating conditions on page 12 , and table 4.3 electrical characteristics on page 13 . ? clarified multiple parameters. ? added 5.1 detailed pin descriptions . ? added 6. packaging including outline and land pattern. revision 0.1 march, 2017 ? initial release. SI3404 data sheet revision history silabs.com | building a more connected world. preliminary rev. 0.5 | 24
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